Variable Impedance Single Pole Double Throw CMOS Switch

ABSTRACT

A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

BACKGROUND

The present disclosure generally relates to a semiconductor switch, andparticularly to a semiconductor switch circuit including a variableimpedance single pole double throw (SPDT) switch.

A complementary metal oxide semiconductor (CMOS) switch can be employedto connect a semiconductor circuit to an antenna. The antenna can beemployed to broadcast a signal that the semiconductor circuit generates,or can be employed to receive a signal to be relayed to thesemiconductor circuit. Depending on whether the antenna broadcasts asignal or receives a signal, different signal paths are required betweenthe antenna and the semiconductor circuit.

A single pole double throw (SPDT) switch is typically employed betweenthe semiconductor circuit and the two signal paths to the antenna. Afirst path can include a series connection of a drive amplifier and ahigh power amplifier. To broadcast a signal, a signal generated by asection of the semiconductor circuit configured to encode the signalpasses through the drive amplifier, the high power amplifier, and theSPDT switch, and subsequently reaches the antenna, which broadcasts thesignal. The node between the SPDT switch and the high power amplifier istypically referred to as a transmitter node TX. A second path caninclude a series connection of a limiter and a low noise amplifier. Toreceive a signal, a signal captured by the antenna passes the SPDTswitch, and then through the limiter and the low noise amplifier,arriving at a section the semiconductor circuit configured to decode thesignal. The node between the SPDT switch and the limiter is typicallyreferred to as a reception node RX.

Referring to FIG. 1, a prior art single pole double throw (SPDT) switchconfigured for use with an antenna includes a serial connection of afirst transmission-side transistor MT1 and a reception-side transistorMR1 between a transmission node TX and a reception node RX. An antennais connected to a node between the drains of the first transmission-sidetransistor MT1 and the reception-side transistor MR1. The gate and bodyof the first transmission-side transistor MT1 have fixed impedances,i.e., the resistance of a gate-side resistor R_(g) and the resistance ofthe body-side resistor R_(w). Likewise, the gate and body of the firstreception-side transistor MR1 have fixed impedances as well.

Typically, a second transmission-side transistor MT2 is provided betweenthe transmission node TX and electrical ground. The body of the secondtransmission-side transistor MT2 is grounded through a body-sideresistor R_(w). Likewise, a second reception-side transistor MR2 isprovided between the reception node RX and electrical ground. The bodyof the second reception-side transistor MR2 is grounded through abody-side resistor R_(w).

The first transmission-side transistor MT1 and the first reception-sidetransistor MR1 operate complementarily, i.e., one is on and the other isoff during normal operation. Likewise, the second transmission-sidetransistor MT2 and the second reception-side transistor MR2 operatecomplementarily. During a transmission mode, the first transmission-sidetransistor MT1 and the second reception-side transistor MR2 are turnedon, and the first reception-side transistor MR1 and the secondtransmission-side transistor MT2 are turned off. A signal path from thetransmission node TX to the antenna is connected during the transmissionmode, while the first reception-side transistor MR1 provides electricalisolation between the antenna and the reception node RX. During areception mode, the first transmission-side transistor MT1 and thesecond reception-side transistor MR2 are turned off, and the firstreception-side transistor MR1 and the second transmission-sidetransistor MT2 are turned on. A signal path from the reception node RXto the antenna is connected during the reception mode, while the firsttransmission-side transistor MT1 provides electrical isolation betweenthe antenna and the transmission node TX.

The SPDT switch needs to transmit a signal through one path, whiledecoupling the signal in the other path in order to provide a highfidelity signal, i.e., a signal with a high signal-to-noise ratio. Inorder to broadcast a signal with high fidelity, an SPDT switch needs tominimize signal loss connecting to the transmitter node TX to passsignal to the antenna, while suppressing and electrically isolating thereception node RX. In order to preserve the fidelity of the signalreceived from the antenna, an SPDT switch needs to minimize signal lossconnecting to the reception node RX to receiver the signal from theantenna, while suppressing and electrically isolating the transmitternode TX. The signal loss in a signal path due to the presence of thefirst transmission-side transistor MT1 or the first reception-sidetransistor MR1 is referred to as insertion loss. Ideally, the insertionloss should be zero decibel. The attenuation of the electricallyisolated signal across the source and the drain of a turned-off firsttransistor, i.e., either the first transmission-side transistor MT1 orthe first reception-side transistor MR1 in a turned-off state, isreferred to as noise isolation. Ideally, the noise isolation should be alarge negative number in decibels. An ideal SPDT switch thus needs toprovide low signal loss and effective noise isolation at the same time.In the prior art SPDT switch of FIG. 1, the fixed impedance valueswithin the circuit place a limit on the insertion loss and noiseisolation.

BRIEF SUMMARY

A single pole double throw (SPDT) semiconductor switch includes a seriesconnection of a first transmitter-side transistor and a firstreception-side transistor between a transmitter node and a receptionnode. An antenna is attached to the node between the two firsttransistors. Each of the two first transistors is provided with agate-side variable impedance circuit, which provides a variableimpedance connection between a complementary pair of gate controlsignals. Further, the body of each first transistor can be connected toa body bias control signal through a body-side variable impedancecircuit. In addition, the transmitter node is connected to electricalground through a second transmitter-side transistor, and the receptionnode is connected to electrical ground through a second reception-sidetransistor. Each of the second transistors can have a body bias that istied to the body bias control signals for the first transistors so thatswitched-off transistors provide enhanced electrical isolation.

According to another aspect of the present disclosure, a single poledouble throw (SPDT) switch circuit is provided, which includes: a serialconnection of a first transmission-side transistor and a firstreception-side transistor between a transmission node and a receptionnode; an antenna connected to a node between the first transmission-sidetransistor and the first reception-side transistor; a first variableimpedance circuit connected to a gate of the first transmission-sidetransistor and configured to provide a first high impedance state or afirst low impedance state depending on a first impedance controlvoltage; and a second variable impedance circuit connected to a gate ofthe first reception-side transistor and configured to provide a secondhigh impedance state or a second low impedance state depending on asecond impedance control voltage.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a schematic of a circuit incorporating a prior art single poledouble throw (SPDT) switch configured for use with an antenna.

FIG. 2 is a schematic of a circuit incorporating an SPDT switchaccording to an embodiment of the present disclosure.

FIG. 3 is a vertical cross-sectional view of an exemplary semiconductordevice with a variable gate impedance and a variable body impedance andbody biasing capabilities.

FIG. 4 is an equivalent circuit schematic of the circuit of FIG. 2 whilea signal from a transmitter node TX is routed to an antenna and areception node RX is electrically isolated.

FIG. 5 is an equivalent circuit schematic of the circuit of FIG. 2 whilea signal from the antenna is routed to the reception node RX and thetransmitter node TX is electrically isolated.

FIG. 6 is a plot of simulation results that compare the insertion lossand noise isolation of the prior art SPDT switch of FIG. 1 and the SPDTswitch of FIG. 2.

DETAILED DESCRIPTION

As stated above, the present disclosure relates to a semiconductorswitch circuit including a variable impedance single pole double throw(SPDT) switch, which is now described in detail with accompanyingfigures. It is noted that like reference numerals refer to like elementsacross different embodiments. The drawings are not necessarily drawn toscale. The drawings are not necessarily drawn to scale.

Referring to FIG. 2, a circuit incorporating an SPDT switch according toan embodiment of the present disclosure is shown. The SPDT switchprovides an electrically conductive signal path between the antenna andone of the transmission node TX and the reception node RX. Thetransmission node TX is connected to a semiconductor circuit (not shown)that generates signals to be passed to the transmission node TX and thento the antenna. The reception node RX is connected to anothersemiconductor circuit (not shown) that receives and amplifies the signalat the reception node RX.

The SPDT switch includes a serial connection of a firsttransmission-side transistor MT1 and a first reception-side transistorMR1 located between the transmission node TX and the reception node RX.The source of the first transmission-side transistor MT1 can be directlyconnected to the transmission node TX, i.e., connected without anyintervening electrical component between the source of the firsttransmission-side transistor MT1 and the transmission node TX. Thesource of the first reception-side transistor MR1 can be directlyconnected to the reception node RX, i.e., connected without anyintervening electrical component between the source of the firstreception-side transistor MR1 and the reception node RX. The antenna isconnected to the node between the first transmission-side transistor MT1and the first reception-side transistor MR1, i.e., the node between thedrain of the first transmission-side transistor MT1 and the drain of thefirst reception-side transistor MR1. This node is referred to as anantenna node, and is directly connected to the drains of the firsttransmission-side transistor MT1 and the first reception-side transistorMR1.

The SPDT switch electrically connects the antenna to one of thetransmission node TX and the reception node RX, while electricallyisolating the antenna from the other of the transmission node TX and thereception node RX. During normal operation of the SPDT switch, one ofthe first transmission-side transistor MT1 and the first reception-sidetransistor MR1 is turned on and the other of the first transmission-sidetransistor MT1 and the first reception-side transistor MR1 is turnedoff. Specifically, during operation of the SPDT switch in a transmissionmode, the first transmission-side transistor MT1 is turned on, and thefirst reception-side transistor MR1 is turned off. Parasitic electricalcoupling through the first reception-side transistor MR1 in theturned-off state introduces noise from the reception node RX into theantenna node. Further, during operation of the SPDT switch in areception mode, the first reception-side transistor MR1 is turned on,and the first transmission-side transistor MT1 is turned off. Parasiticelectrical coupling through the first transmission-side transistor MT1in the turned-off state introduces noise from the transmission node TXinto the antenna node.

A first variable impedance circuit VIC1 is connected to the gate of thefirst transmission-side transistor MT1. The first variable impedancecircuit VIC1 is configured to provide a first high impedance state or afirst low impedance state depending on a first impedance control voltageapplied to the first variable impedance circuit VIC1. A second variableimpedance circuit VIC2 is connected to the gate of the firstreception-side transistor MR1. The second variable impedance circuitVIC2 is configured to provide a second high impedance state or a secondlow impedance state depending on a second impedance control voltageapplied to the second variable impedance circuit VIC2.

The first variable impedance circuit VIC1 is located between a firstgate control node GC1 and the gate of the first transmission-sidetransistor MT1, and the second variable impedance circuit VIC2 islocated between a second gate control node GC2 and the gate of the firstreception-side transistor MR1. The first gate control node GC1 andsecond gate control node GC2 are configured to be provided with acomplementary pair of gate control signals. The complementary pair ofgate control signals include a first gate control signal V_(ctrl) and asecond gate control voltage signal V_(ctrlb).

The first transmission-side transistor MT1 and the first reception-sidetransistor MR1 can be field effect transistors of the same type, i.e., apair of n-type field effect transistors or a pair of p-type field effecttransistors. Thus, both the first transmission-side transistor MT1 andthe first reception-side transistor MR1 are configured to be turned onor turned off by the same type of gate control voltages. Specifically,if the first transmission-side transistor MT1 and the firstreception-side transistor MR1 are n-type field effect transistors, thefirst transmission-side transistor MT1 and the first reception-sidetransistor MR1 are configured to be turned on when a first voltage isapplied to a gate and turned off when a second voltage is applied to thegate, in which the first voltage is more positive than the secondvoltage. Typically, the first voltage is a positive voltage and thesecond voltage is zero volt, i.e., the same as the voltage of electricalground. Conversely, if the first transmission-side transistor MT1 andthe first reception-side transistor MR1 are p-type field effecttransistors, the first transmission-side transistor MT1 and the firstreception-side transistor MR1 are configured to be turned on when afirst voltage is applied to a gate and turned off when a second voltageis applied to the gate, in which the first voltage is more negative thanthe second voltage. Typically, the first voltage is zero volt and thesecond voltage is a positive voltage.

The first gate control signal V_(ctrl) and a second gate control voltagesignal V_(ctrlb) are “complementary” because one of the first gatecontrol signal V_(ctrl) and a second gate control voltage signalV_(ctrlb) turns on a transistor, which is one of the firsttransmission-side transistor MT1 and the first reception-side transistorMR1, to which the signal is applied, while the other of the first gatecontrol signal V_(ctrl) and a second gate control voltage signalV_(ctrlb) turns off a transistor, which is the other of the firsttransmission-side transistor MT1 and the first reception-side transistorMR1, to which the signal is applied. Thus, the SPDT switch circuit isconfigured to alternatively provide either a combination of the firsthigh impedance state and the second low impedance state, or acombination of the first low impedance state and the second highimpedance state.

In one embodiment, the first variable impedance circuit VIC1 includes aparallel connection of a first gate-control transistor MG1 and a firstgate-side resistor R_(g1) between the first gate control node GC1 andthe gate of the first transmission-side transistor MT1, and the secondvariable impedance circuit VIC2 includes a parallel connection of asecond gate-control transistor MG2 and a second gate-side resistorR_(g2) between the second gate-control node and the gate of the secondtransmission-side transistor MT2. The first variable impedance circuitVIC1 can further include a first gate-control-side resistor R_(sg1)connected to the gate of the first gate-control transistor MG1, and thesecond variable impedance circuit VIC2 can further include a secondgate-control-side resistor R_(sg2) connected to the gate of the secondgate-control transistor MG2. The first gate-control-side resistorR_(sg1) is located between a first variable impedance control node VC1and the gate of the first gate-control transistor MG1. The secondgate-control-side resistor R_(sg2) is located between a second variableimpedance control node VC2 and the gate of the second gate-controltransistor MG2.

In one embodiment, the first impedance control voltage applied to thefirst variable impedance circuit VIC1 can be the same as the second gatecontrol signal V_(ctrlb), and the second impedance control voltageapplied to the second variable impedance circuit VIC2 can be the same asthe first gate control signal V_(ctrl). The first gate control node GC1and the gate of the second gate-control transistor MG2 are provided withthe first gate control signal V_(ctrl), and the second gate control nodeGC2 and the gate of the first gate-control transistor MG1 are providedwith the second gate control signal V_(ctrlb). Thus, the pair of thefirst gate control signal V_(ctrl), and the second gate control signalV_(ctrlb) determines not only the voltage potential at the gates of thefirst transmission-side transistor MT1 and the second transmission-sidetransistor MT2, but also the impedance at the gate of the firsttransmission-side transistor MT1 and impedance at the gate of the secondtransmission-side transistor MT2.

Specifically, the first high impedance state provides an impedance ofthe first gate-side resistor R_(g1), and the first low impedance stateprovides an impedance of an on-state of the first gate-controltransistor MG1. Correspondingly, the second high impedance stateprovides an impedance of the second gate-side resistor R_(g2), and thesecond low impedance state provides an impedance of an on-state of thesecond gate-control transistor MG2. Each of the first gate-side resistorR_(g1) and the second gate-side resistor R_(g2) has a resistance from 1kOhms to 10 kOhms, and typically from 2 kOhms to 20 kOhms, althoughlesser and greater resistances can also be employed. The impedance ofthe on-state of the first gate-control transistor MG1 and the impedanceof the on-state of the second gate-control transistor MG2 can be from 1Ohm to 100 Ohms, although lesser and greater impedances can also beemployed. The bodies of the first gate-control transistor MG1 and thesecond gate-control transistor MG1 are connected to electrical ground bya well resistance R_(w), which can be from 1 kOhms to 10 kOhms, althoughlesser and greater resistances can also be employed.

The SPDT switch can further include additional variable impedancecircuits. Specifically, the SPDT switch can include a third variableimpedance circuit VIC3 connected to the body of the firsttransmission-side transistor MT1 and a fourth variable impedance circuitVIC4 connected to the body of the first reception-side transistor MR1.The third variable impedance circuit VIC3 is configured to provide athird high impedance state or a third low impedance state depending onan impedance control voltage, which can be the same as the firstimpedance control voltage. In other words, the first impedance controlvoltage can be applied to the first variable impedance circuit VIC1 andthe third variable impedance circuit VIC3. As discussed above, the firstimpedance control voltage can be the same as the second gate controlsignal V_(ctrlb). The fourth variable impedance circuit VIC4 isconfigured to provide a fourth high impedance state or a low impedancestate depending on an impedance control voltage, which can be the sameas the second impedance control voltage. In other words, the secondimpedance control voltage can be applied to the second variableimpedance circuit VIC2 and the fourth variable impedance circuit VIC4.As discussed above, the second impedance control voltage can be the sameas the first gate control signal V_(ctrl).

By cross-coupling of impedance control voltages between the first andsecond variable impedance circuits (VIC1 and VIC2) and the third andfourth variable impedance circuits (VIC3 and VIC4) and use of acomplementary pair of voltage signals for the first gate control signalV_(ctrl) and the second gate control signal V_(ctrlb), the SPDT switchcircuit can be configured to alternatively provide either a combinationof the first high impedance state the second low impedance state, thethird high impedance state, and the fourth low impedance state, or acombination of the first low impedance state, the second high impedancestate, the third low impedance state, and the fourth high impedancestate.

The third variable impedance circuit VIC3 is located between a firstbody bias control node BBC1 and the body of the first transmission-sidetransistor MT1, and the fourth variable impedance circuit VIC4 islocated between a second body bias control node BBC2 and the body of thefirst reception-side transistor MR1. The first and second body biascontrol nodes (BBC1 and BBC2) can be configured to be provided with acomplementary pair of body bias control signals. In other words, one ofthe first and second body bias control nodes (BBC1 and BBC2) is providedwith one of two different preset voltages, and the other of the firstand second body bias control nodes (BBC1 and BBC2) is provided with theother of the two different preset voltages.

In one embodiment, the third variable impedance circuit VIC3 includes aparallel connection of a first body bias control transistor MB1 and afirst body-side resistor between the first body bias control node BBC1and the body of the first transmission-side transistor MT1.Correspondingly, the fourth variable impedance circuit VIC4 includes aparallel connection of a second body bias control transistor MB2 and asecond body-side resistor between the second body bias control node BBC2and the body of the second transmission-side transistor MT2.

The complementary pair of body bias control signals include a first bodybias control signal V_(b1) and a second body bias control signal V_(b2).The first body bias control node BBC1 is provided with the first bodybias control signal V_(b1), and the second body bias control node BBC2is provided with the second body bias control signal V_(b2).

In an embodiment in which the first transmission-side transistor MT1 andthe first reception-side transistor MR1 are n-type field effecttransistors, the first body bias control signal V_(b1) can be zero voltif the third variable impedance circuit VIC3 is in the third highimpedance state, and the second body bias control signal V_(b2) can bezero volt if the fourth variable impedance circuit VIC4 is in the fourthhigh impedance state. The third variable impedance circuit VIC3 is inthe third high impedance state when the first transmission-sidetransistor MT1 is turned on, and is in the third low impedance statewhen the first transmission-side transistor MT1 is turned off. Thefourth variable impedance circuit VIC4 is in the fourth high impedancestate when the first reception-side transistor MR1 is turned on, and isin the fourth low impedance state when the first reception-sidetransistor MR1 is turned off

If the third variable impedance circuit VIC3 is in the third lowimpedance state and the first transmission-side transistor MT1 is turnedoff, the first body bias control signal V_(b1) is a first non-zerovoltage that reduces a source-drain leakage current of the firsttransmission-side transistor MT1 compared to a state in which the firstbody bias control signal V_(b1) is zero volt. If the firsttransmission-side transistor MT1 is an n-type transistor, the firstnon-zero voltage is a negate voltage having a value between 0 V and −2V. If the fourth variable impedance circuit VIC4 is in the fourth lowimpedance state and the first reception-side transistor MR1 is turnedoff, the second body bias control signal V_(b2) is a second non-zerovoltage that reduces a source-drain leakage current of the firstreception-side transistor MR1 compared to a state in which the secondbody bias control signal V_(b2) is zero volt. If the firstreception-side transistor MR1 is an n-type transistor, the secondnon-zero voltage is a negate voltage having a value between 0 V and −2V.

The first body bias control signal V_(b1) is zero volt when the thirdvariable impedance circuit VIC3 is in the third high impedance state,the first body bias control signal V_(b1) is the first non-zero voltagewhen the third variable impedance circuit VIC3 is in the third lowimpedance state. The first non-zero voltage drives the firsttransmission-side transistor MT1 into a deep isolation mode, in whichthe voltage of the body of the first transmission-side transistor MT1 ismore negative than a normal off state in which the body of the firsttransmission-side transistor MT1 would be at zero volt. The second bodybias control signal V_(b2) is zero volt when the fourth variableimpedance circuit VIC4 is in the fourth high impedance state, and thesecond body bias control signal V_(b2) is the second non-zero voltagewhen the fourth variable impedance circuit VIC4 is in the fourth lowimpedance state. The second non-zero voltage drives the firstreception-side transistor MR1 into a deep isolation mode, in which thevoltage of the body of the first reception-side transistor MR1 is morenegative than a normal off state in which the body of the firstreception-side transistor MR1 would be at zero volt.

The third variable impedance circuit VIC3 can include a parallelconnection of a first body bias control transistor MB1 and a firstbody-side resistor R_(b1) between the first body bias control node BBC1and the body of the first transmission-side transistor MT1, and thefourth variable impedance circuit VIC4 can include a parallel connectionof a second body bias control transistor MB2 and a second body-sideresistor R_(b2) between the second body bias control node BBC2 and thebody of the second transmission-side transistor MT2. The first body-sideresistor R_(b1) and the second body-side resistor R_(b2) can be providedin the form of a well resistance in a transistor on a triple wellstructure illustrated in FIG. 3.

FIG. 3 schematically illustrates an n-type transistor built on a triplewell structure in a semiconductor substrate 8 with a gate bias and abody bias of the present disclosure. The semiconductor substrateincludes a p-type substrate layer 10 embedding an n-type well 20. Thep-type substrate layer 10 is electrically grounded, and the n-type well20 is biased at a positive voltage V_(DD) through an n-doped contactregion 22. A p-type well 30 is embedded in the n-type well 20. A p-dopedcontact region 32 can be formed in the p-type well 30. A portion of thep-type well 30 forms the body of the n-type transistor. The p-type well30 is biased with the first body bias control signal V_(b1) or thesecond body bias control signal V_(b2) through the third variableimpedance circuit VIC3 or the fourth variable impedance circuit VIC4.

An n-doped source 34 and an n-doped drain 36 are formed in the p-typewell 30. A gate dielectric 50 and a gate electrode 52 are formed overthe channel region between the n-doped source 34 and the n-doped drain36. The gate electrode 52 is biased with the first gate control signalV_(ctrl) or the second gate control signal V_(ctrlb) through the firstvariable impedance circuit VIC1 or the second variable impedance circuitVIC2. The n-doped source 34 is electrically connected to the source nodeV_(s), which corresponds to the transmission node TX or the receptionnode RX in the circuit of FIG. 2. The n-doped drain 36 is electricallyconnected to the drain node V_(d), which corresponds to the antenna nodein the circuit of FIG. 2.

Referring back to FIG. 2, the third high impedance state can provide animpedance of the first body-side resistor R_(b1), and the third lowimpedance state can provide an impedance of the on-state of the firstbody bias control transistor MB1. Further, the fourth high impedancestate can provide an impedance of the second body-side resistor R_(b2),and the fourth low impedance state can provide an impedance of theon-state of the second body bias control transistor MB2.

The impedance control signals for the body bias control transistors (MB1and MB2) can be cross-coupled to the complementary gate control signals,i.e., the first gate control signal V_(ctrl) and the second gate controlsignal V_(ctrlb). The gate of the first transmission-side transistor MT1and the gate of the second body bias control transistor MB2 are providedwith the first gate control signal V_(ctrl), and the gate of the secondtransmission-side transistor MT2 and the gate of the first body biascontrol transistor MB1 are provided with a second gate control signalV_(ctrlb).

The third variable impedance circuit VIC3 can further include a firstbody-control-side resistor R_(bg1) connected to a gate of the first bodybias control transistor MB1, and the fourth variable impedance circuitVIC4 further includes a second body-control-side resistor connected to agate of the second body bias control transistor MB2. The firstbody-control-side resistor R_(bg1) is located between a third variableimpedance control node VC3 and the gate of the first body bias controltransistor MB1. The second body-control-side resistor R_(bg2) is locatedbetween a fourth variable impedance control node VC4 and the gate of thesecond body bias control transistor MB2.

In one embodiment, the impedance control voltage applied to the thirdvariable impedance control node VC3 can be the same as the firstimpedance control voltage applied to the first variable impedancecontrol node VC1, i.e., the second gate control signal V_(ctrlb) that isapplied to the gate of the first reception-side transistor MR1. Theimpedance control voltage applied to the fourth variable impedancecontrol node VC4 can be the same as the second impedance control voltageapplied to the second variable impedance control node VC2, i.e., thefirst gate control signal V_(ctrl) that is applied to the gate of thefirst transmission-side transistor MT1. Thus, the pair of the first gatecontrol signal V_(ctrl), and the second gate control signal V_(ctrlb)determines not only the voltage potential at the gates of the firsttransmission-side transistor MT1 and the second transmission-sidetransistor MT2, but also the impedance at the body of the firsttransmission-side transistor MT1 and impedance at the body of the secondtransmission-side transistor MT2 in synchronization with the control ofthe impedance at the gate of the first transmission-side transistor MT1(repetition with the red line).

Each of the first body-control-side resistor R_(bg1) and the secondbody-control-side resistor R_(bg2) has a resistance from 1 kOhms to 10kOhms, and typically from 2 kOhms to 20 kOhms, although lesser andgreater resistances can also be employed. The impedance of the on-stateof the first body bias control transistor MB1 and the impedance of theon-state of the second body bias control transistor MB2 can be from 1Ohm to 100 Ohms, although lesser and greater impedances can also beemployed. The bodies of the first body bias control transistor MB1 andthe second body bias control transistor MB2 are connected to electricalground by a well resistance R_(w), which can be from 1 kOhms to 10kOhms, and typically from 2 kOhms to 20 kOhms, although lesser andgreater resistances can also be employed.

The SPDT switch further includes a second transmission-side transistorMT2 connected between the transmission node and electrical ground and asecond reception-side transistor MR2 connected between the receptionnode and electrical ground.

In one embodiment, the body of the second transmission-side transistorMT2 can be electrically connected to the second body bias control nodeBBC2, and the body of the second reception-side transistor MR2 can beelectrically connected to the first body bias control node BBC1.

The cross-coupling of the body bias signals between the first and secondbody bias control transistors (MB1 and MB2) and the secondtransmission-side transistor MT2 and the second reception-sidetransistor MR2 can enhance signal isolation for transistors in theoff-state. Specifically, the first body bias control node BBC1 isprovided with the first body bias control signal V_(b1), and the secondbody bias control node BBC2 is provided with the second body biascontrol signal V_(b2). The first body bias control signal V_(b1) is zerovolt if the third variable impedance circuit VIC3 is in the third highimpedance state, and the second body bias control signal V_(b2) is zerovolt if the fourth variable impedance circuit VIC4 is in the fourth highimpedance state.

Referring to FIG. 4, an equivalent circuit schematic of the circuit ofFIG. 2 is illustrated for a transmission mode, i.e., while a signal froma transmitter node TX is routed to an antenna and the reception node RXis electrically isolated. In the transmission mode, the firsttransmission-side transistor MT1, the second reception-side transistorMR2, the second gate-control transistor MG2, and the second body biascontrol transistor MB2 are turned on, and the first reception-sidetransistor MR1, the second transmission-side transistor MT2, the firstgate-control transistor MG1, and the first body bias control transistorMB1 are turned off.

Since the resistance of the second gate-control transistor MG2 in the onstate, and the resistance of the second body bias control transistor MB2in the on state are negligible compared with the resistance of thesecond gate-side resistor R_(g2) and the second body-side resistorR_(b2), respectively, the second variable impedance circuit VIC2 and thefourth variable impedance circuit VIC4 can be replaced with twoturned-on transistors, which are approximated by a short circuit, i.e.,a direct electrical connection between the second gate control node GC2and the gate of the first reception-side transistor MR1 and a directelectrical connection between the second body bias control node BBC2 andthe body of the first reception-side transistor MR1.

Further, since the resistance of the first gate-control transistor MG1in the off state, and the resistance of the first body bias controltransistor MB1 in the off state are orders of magnitude greater than theresistance of the first gate-side resistor R_(g1) and the firstbody-side resistor R_(b1), respectively, the first variable impedancecircuit VIC1 and the third variable impedance circuit VIC3 can bereplaced the first gate-side resistor R_(g1) and the first body-sideresistor R_(b1), respectively.

The large impedance at the gate and body of the first transmission-sidetransistor MT1, which is at least one order of magnitude greater thanon-state resistance of a transistor, reduces the insertion loss of thefirst transmission-side transistor MT1 while the first transmission-sidetransistor MT1 is turned on. Further, the small impedance at the gateand body of the first reception-side transistor MR1, which are theon-state resistances of transistors, reduces coupling of spurioussignals at the first reception-side transistor MR1, i.e., enhances thesignal isolation at the first reception-side transistor MR1. Inaddition, the negative voltage bias applied from the second body biasvoltage node BB2 to the body of the first reception-side transistor MR1and the second transmission-side transistor MT2 further reducesparasitic coupling of the signals at the first reception-side transistorMR1 and the second transmission-side transistor MT2.

Referring to FIG. 5, an equivalent circuit schematic of the circuit ofFIG. 2 is illustrated for a reception mode, i.e., while a signal fromthe antenna is routed to the reception node RX and the transmission nodeTX is electrically isolated. In the reception mode, the firstreception-side transistor MR1, the second transmission-side transistorMT2, the first gate-control transistor MG1, and the first body biascontrol transistor MB1 are turned on, and the first transmission-sidetransistor MT1, the second reception-side transistor MR2, the secondgate-control transistor MG2, and the second body bias control transistorMB2 are turned off.

Since the resistance of the first gate-control transistor MG1 in the onstate, and the resistance of the first body bias control transistor MB1in the on state are negligible compared with the resistance of the firstgate-side resistor R_(g1) and the first body-side resistor R_(b1),respectively, the first variable impedance circuit VIC1 and the thirdvariable impedance circuit VIC3 can be replaced with two turned-ontransistors, which are approximated by a short circuit, i.e., a directelectrical connection between the first gate control node GC1 and thegate of the first transmission-side transistor MT1 and a directelectrical connection between the first body bias control node BBC1 andthe body of the first transmission-side transistor MT1.

Further, since the resistance of the second gate-control transistor MG2in the off state, and the resistance of the second body bias controltransistor MB2 in the off state are orders of magnitude greater than theresistance of the second gate-side resistor R_(g2) and the secondbody-side resistor R_(b2), respectively, the second variable impedancecircuit VIC2 and the fourth variable impedance circuit VIC4 can bereplaced the second gate-side resistor R_(g2) and the second body-sideresistor R_(b2), respectively.

The large impedance at the gate and body of the first reception-sidetransistor MR1, which is at least one order of magnitude greater thanon-state resistance of a transistor, reduces the insertion loss of thefirst reception-side transistor MR1 while the first reception-sidetransistor MR1 is turned on. Further, the small impedance at the gateand body of the first transmission-side transistor MT1, which are theon-state resistances of transistors, reduces coupling of spurioussignals at the first transmission-side transistor MT1, i.e., enhancesthe signal isolation at the first transmission-side transistor MT1. Inaddition, the negative voltage bias applied from the first body biasvoltage node BB1 to the body of the first transmission-side transistorMT1 and the second reception-side transistor MR2 further reducesparasitic coupling of the signals at the first transmission-sidetransistor MT1 and the second reception-side transistor MR2.

Referring to FIG. 6, simulation results compare the insertion loss andnoise isolation of the prior art SPDT switch of FIG. 1 and the SPDTswitch of FIG. 2. For the purpose of simulation, all resistors wereassumed to have a resistance of 5 kOhms. Transistor parameters wereassigned based on specifications of typical state of the art n-typemetal-oxide-semiconductor field effect transistors (MOSFETs).

A first curve 610 connects simulation data points representing the noiseisolation for the prior art SPDT switch of FIG. 1. A second curve 620connects simulation data points representing the noise isolation for theSPDT switch of the present disclosure illustrated in FIG. 2. The secondcurve 620 shows an enhancement in the noise isolation by at least 30decibels in the frequency range between 2 GHz and 40 GHz, i.e., providesbetter noise isolation by suppressing parasitic signal couplings.

A third curve 630 connects simulation data points representing theinsertion loss for the prior art SPDT switch of FIG. 1. A fourth curve640 connects simulation data points representing the insertion loss forthe SPDT switch of the present disclosure illustrated in FIG. 2. Thefourth curve 640 shows an enhancement in the insertion loss by at least0.15 decibel in the frequency range between 2 GHz and 40 GHz, i.e.,provides less insertion loss during transmission of signals.

While the present disclosure has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present disclosure. It is therefore intended that the presentdisclosure not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A single pole double throw (SPDT) switch circuit comprising: a serialconnection of a first transmission-side transistor and a firstreception-side transistor between a transmission node and a receptionnode; an antenna connected to a node between said firsttransmission-side transistor and said first reception-side transistor; afirst variable impedance circuit connected to a gate of said firsttransmission-side transistor and configured to provide a first highimpedance state or a first low impedance state depending on a firstimpedance control voltage; and a second variable impedance circuitconnected to a gate of said first reception-side transistor andconfigured to provide a second high impedance state or a second lowimpedance state depending on a second impedance control voltage.
 2. TheSPDT switch circuit of claim 1, wherein said SPDT switch circuit isconfigured to alternatively provide either a combination of said firsthigh impedance state and said second low impedance state or acombination of said first low impedance state and said second highimpedance state.
 3. The SPDT switch circuit of claim 2, wherein saidfirst variable impedance circuit is located between a first gate controlnode and said gate of said first transmission-side transistor, and saidsecond variable impedance circuit is located between a second gatecontrol node and said gate of said first reception-side transistor, andsaid first and second gate control nodes are configured to be providedwith a complementary pair of gate control signals.
 4. The SPDT switchcircuit of claim 3, wherein said first variable impedance circuitincludes a parallel connection of a first gate-control transistor MG1and a first gate-side resistor between said first gate control node andsaid gate of said first transmission-side transistor, and said secondvariable impedance circuit includes a parallel connection of a secondgate-control transistor and a second gate-side resistor between saidsecond gate-control node and said gate of said second transmission-sidetransistor.
 5. The SPDT switch circuit of claim 4, wherein saidcomplementary pair of gate control signals include a first gate controlsignal V_(ctrl) and a second gate control signal V_(ctrlb), said firstgate control node and a gate of said second gate-control transistor areprovided with said first gate control signal V_(ctrl), and said secondgate control node and a gate of said first gate-control transistor areprovided with said second gate control signal V_(ctrl).
 6. The SPDTswitch circuit of claim 4, wherein said first high impedance stateprovides an impedance of said first gate-side resistor, said first lowimpedance state provides an impedance of an on-state of said firstgate-control transistor MG1, said second high impedance state providesan impedance of said second gate-side resistor, and said second lowimpedance state provides an impedance of an on-state of said secondgate-control transistor.
 7. The SPDT switch circuit of claim 4, whereinsaid first variable impedance circuit further includes a firstgate-control-side resistor connected to a gate of said firstgate-control transistor, and said second variable impedance circuitfurther includes a second gate-control-side resistor connected to a gateof said second gate-control transistor.
 8. The SPDT switch circuit ofclaim 2, further comprising: a third variable impedance circuitconnected to a body of said first transmission-side transistor andconfigured to provide a third high impedance state or a third lowimpedance state depending on said first impedance control voltage,wherein said first impedance control voltage is applied to said thirdvariable impedance circuit; and a fourth variable impedance circuitconnected to a body of said first reception-side transistor andconfigured to provide a fourth high impedance state or a fourth lowimpedance state depending on said second impedance control voltage,wherein said second impedance control voltage is applied to said fourthvariable impedance circuit.
 9. The SPDT switch circuit of claim 8,wherein said SPDT switch circuit is configured to alternatively provideeither a combination of said first high impedance state, said second lowimpedance state, said third high impedance state, and said fourth lowimpedance state, or a combination of said first low impedance state,said second high impedance state, said third low impedance state, andsaid fourth high impedance state.
 10. The SPDT switch circuit of claim9, wherein said third variable impedance circuit is located between afirst body bias control node and said body of said firsttransmission-side transistor, and said fourth variable impedance circuitis located between a second body bias control node and said body of saidfirst reception-side transistor, and said first and second body biascontrol nodes are configured to be provided with a complementary pair ofbody bias control signals.
 11. The SPDT switch circuit of claim 10,wherein said third variable impedance circuit includes a parallelconnection of a first body bias control transistor MB1 and a firstbody-side resistor between said first body bias control node and saidbody of said first transmission-side transistor, and said fourthvariable impedance circuit includes a parallel connection of a secondbody bias control transistor MB2 and a second body-side resistor betweensaid second body bias control node and said body of said secondtransmission-side transistor.
 12. The SPDT switch circuit of claim 11,wherein said complementary pair of body bias control signals include afirst body bias control signal V_(b1) and a second body bias controlsignal V_(b2), said first body bias control node is provided with saidfirst body bias control signal V_(b1), and said second body bias controlnode is provided with said second body bias control signal V_(b2), saidfirst body bias control signal V_(b1) is zero volt if said thirdvariable impedance circuit is in said third high impedance state, andsaid second body bias control signal V_(b2) is zero volt if said fourthvariable impedance circuit is in said fourth high impedance state. 13.The SPDT switch circuit of claim 12, wherein said first body biascontrol signal V_(b1) is a first non-zero voltage if said third variableimpedance circuit is in said third low impedance state, said second bodybias control signal V_(b2) is a second non-zero voltage if said fourthvariable impedance circuit is in said fourth low impedance, said firstnon-zero voltage applied to said first transmission-side transistorreduces a source-drain leakage current of said first transmission-sidetransistor compared to a state in which said first body bias controlsignal V_(b1) is zero volt, and said second non-zero voltage applied tosaid first reception-side transistor reduces a source-drain leakagecurrent of said first reception-side transistor compared to a state inwhich said second body bias control signal V_(b2) is zero volt.
 14. TheSPDT switch circuit of claim 13, wherein said first body bias controlsignal V_(b1) is zero volt when said third variable impedance circuit isin said third high impedance state, said first body bias control signalV_(b1) is said first non-zero voltage when said third variable impedancecircuit is in said third low impedance state, said second body biascontrol signal V_(b2) is zero volt when said fourth variable impedancecircuit is in said fourth high impedance state, and said second bodybias control signal V_(b2) is said second non-zero voltage when saidfourth variable impedance circuit is in said fourth low impedance state.15. The SPDT switch circuit of claim 12, wherein a gate of said firsttransmission-side transistor and a gate of said second body bias controltransistor MB2 are provided with a first gate control signal V_(ctrl),and a gate of said second transmission-side transistor and a gate ofsaid first body bias control transistor MB1 are provided with a secondgate control signal V_(ctrlb), wherein said first gate control signalV_(ctrl) and said second gate control signal V_(ctrlb) are complementarysignals.
 16. The SPDT switch circuit of claim 11, wherein said thirdhigh impedance state provides an impedance of said first body-sideresistor, said third low impedance state provides an impedance of anon-state of said first body bias control transistor MB1, said fourthhigh impedance state provides an impedance of said second body-sideresistor, and said fourth low impedance state provides an impedance ofan on-state of said second body bias control transistor MB2.
 17. TheSPDT switch circuit of claim 11, wherein said third variable impedancecircuit further includes a first body-control-side resistor connected toa gate of said first body bias control transistor MB1, and said fourthvariable impedance circuit further includes a second body-control-sideresistor connected to a gate of said second body bias control transistorMB2.
 18. The SPDT switch circuit of claim 9, further comprising: asecond transmission-side transistor connected between said transmissionnode and electrical ground; and a second reception-side transistorconnected between said reception node and electrical ground.
 19. TheSPDT switch circuit of claim 18, wherein said third variable impedancecircuit includes a parallel connection of a first body bias controltransistor MB1 and a first body-side resistor between said first bodybias control node and said body of said first transmission-sidetransistor, and said fourth variable impedance circuit includes aparallel connection of a second body bias control transistor MB2 and asecond body-side resistor between said second body bias control node andsaid body of said second transmission-side transistor, a body of saidsecond transmission-side transistor is electrically connected to saidsecond body bias control node, and a body of said second reception-sidetransistor is electrically connected to said first body bias controlnode.
 20. The SPDT switch of claim 19, wherein said first body biascontrol node is provided with said first body bias control signalV_(b1), and said second body bias control node is provided with saidsecond body bias control signal V_(b2), said first body bias controlsignal V_(b1) is zero volt if said third variable impedance circuit isin said third high impedance state, said second body bias control signalV_(b2) is zero volt if said fourth variable impedance circuit is in saidfourth high impedance state, said second body bias control signal V_(b2)is a second non-zero voltage if said fourth variable impedance circuitis in said fourth low impedance, said first non-zero voltage applied tosaid first transmission-side transistor reduces a source-drain leakagecurrent of said first transmission-side transistor compared to a statein which said first body bias control signal V_(b1) is zero volt, andsaid second non-zero voltage applied to said first reception-sidetransistor reduces a source-drain leakage current of said firstreception-side transistor compared to a state in which said second bodybias control signal V_(b2) is zero volt.